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OPERATING CHARACTERISTICS Valid over full operating temperature range, T
A
 , V
CC
 = 4.5 to 18 V, C
BYPASS
 = 0.1 糉, unless
otherwise noted
Characteristics
Symbol
Test Conditions
Min.   Typ.   Max.    Unit
Electrical Characteristics
Supply Voltage
V
CC
4.5    
18
V
Supply Current
I
CC

6
10
mA
Supply Zener Clamp Voltage
V
Zsupply
I
CC
 = 18 mA, T
A
 = 25篊, t < 5 min
28


V
Power On Time
1,2,3
t
PO
f
pwm
 = 2 kHz


4
ms
Internal Bandwidth
BW
i
Small signal 3 dB, 100 G
(P-P)
 magnetic input
signal
    400    
Hz
Chopping Frequency
4
f
C
T
A
 = 25癈
    200    
kHz
Output Characteristics
PWMOUT Saturation Voltage
V
SAT
I
OUTSINK
 d 20 mA, PWMOUT transistor on


0.6
V
I
OUTSINK
 d 10 mA, PWMOUT transistor on


0.5
V
PWMOUT Current Limit
I
LIMIT
R
L
 = 0 ?/DIV>
30    60    80
mA
PWMOUT Leakage Current
I
LEAK
VCC = 3.2 V, 0 V d PWMOUT d 24 V, PWMOUT
transistor off
    0.1    10
糀
PWMOUT Zener Clamp Voltage
V
ZOUT
I
OUTSINK
 = I
LIMIT
, T
A
 = 25篊
28


V
PWMOUT Rise Time
2,3
t
r
R = 2 k? C = 20 pF

3

約
PWMOUT Fall Time
2,3
t
f
R= 2 k? C = 20 pF

3

約
Maximum Propagation Delay
2,3
t
pd(max)
    1.5

ms
Response Time
2,3
t
RESPONSE
Impulse magnetic field of 300 G, f
pwm
 = 2 kHz
   
2
ms
Load Resistance (External)
3
R
L
PWMOUT to VCC
2040    

?/DIV>
Load Capacitance (External)
3
C
L
PWMOUT to GND


10
nF
Duty Cycle Jitter
2,3,5
J
D
Measured over 1000 output PWM clock periods,
3 sigma values, Sens = 60 m% / G

    ?.090   % D
Clamp Duty Cycle
3
D
CLP(HIGH)
90

95    % D
D
CLP(LOW)
5

10    % D
Pre-Programming Target
6
Pre-Programming Quiescent Duty Cycle
Output
D
(Q)PRE
B = 0 G, T
A
 = 25癈

52

% D
Pre-Programming Sensitivity
Sens
PRE
T
A
 = 25癈

20
   (m% D)/G
Pre-Programming PWM Output Carrier
Frequency
f
PWMPRE
T
A
 = 25癈
    2.8

kHz
Quiescent Duty Cycle Programming
Initial Quiescent Duty Cycle Output
D
(Q)init
T
A
 = 25癈
   D
(Q)PRE

% D
Guaranteed Quiescent Duty Cycle
Output Range
7
D
(Q)
T
A
 = 25癈
40

60    % D
Quiescent Duty Cycle Output
Programming Bits

9

bit
Average Quiescent Duty Cycle Output
Step Size
8,9
Step
D(Q)
T
A
 = 25癈
0.085   0.100   0.115    % D
Quiescent Duty Cycle Output
Programming Resolution
10
Err
PGD(Q)
T
A
 = 25癈

Step
D(Q)
 
??. 5

% D
High Precision Linear Hall-Effect Sensor IC
With an Open Drain Pulse Width Modulated Output
A1356
3
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
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